Monday, January 23, 2006
Ok, it is another course project again. I think this post can be useful for digital designers. "Logical effort" is a technique which can be used in order to find proper sizing of logic gates in a digital design. In "Computer Arithmetic Algorithms" course, which was given by Oscar, I tried to attack CMOS 4-2 compressors using logical effort. You can take a look at my report if you are working with digital gates.