Monday, June 27, 2005

Synchronous Latency-Insensitive Design

Anders Edman and Christer Svensson, sometimes ago proposed "Synchronous Latency-Insensitive Design" (SLID) concept using FIFO structure [1]. The idea is to partition a big chip into isochronous regions. An isochronous region can be defined as a region in which clock can be assumed to be synchronous. It exactly means that clock skews in an isochronous region are not considerable comparing to clock period. Such a region is limited from size point of view. SLID is introduced to create communication between isochronous regions by adding a fixed latency. This latency is predictable because it is decided by designer in advance then all clock skews can be absorbed by this latency. It means that whole design consists of synchronous regions which are communicating with a fixed and specified latency and the design is latency-insensitive.
SLID concept can be generalized for the case that there are different regions in a design which are working with different frequencies. The only criterion is that frequencies should be rationally-related. The idea behind this concept is going to be published in IEEE International System-on-Chip Conference (SoCC) this year [2]. In this concept rate multipliers [3] are used to create communication between isochronous regions.

[1] A. Edman and C. Svensson, "Timing closure through a globally synchronous, timing partitioned design methodology," 41st Proc. Design Automation Conference (DAC), 2004, pp. 71-74
[2] A. Edman, C. Svensson and B. Mesgarzadeh, "Synchronous latency-insensitive design for multiple clock domain," IEEE Intl. SoC Conference, 25-28 Sept. 2005, Washington DC. USA. (To be presented)
[3] A. Chakraborty and M. R. Greensreet, "Efficient self-timed interfaces for crossing clock domains," Proc. Intl. Symposium on Asynchronous Circuits and Systems, 2003, pp. 78-88