Synchronous Latency-Insensitive Design
SLID concept can be generalized for the case that there are different regions in a design which are working with different frequencies. The only criterion is that frequencies should be rationally-related. The idea behind this concept is going to be published in IEEE International System-on-Chip Conference (SoCC) this year . In this concept rate multipliers  are used to create communication between isochronous regions.
 A. Edman and C. Svensson, "Timing closure through a globally synchronous, timing partitioned design methodology," 41st Proc. Design Automation Conference (DAC), 2004, pp. 71-74
 A. Edman, C. Svensson and B. Mesgarzadeh, "Synchronous latency-insensitive design for multiple clock domain," IEEE Intl. SoC Conference, 25-28 Sept. 2005, Washington DC. USA. (To be presented)
 A. Chakraborty and M. R. Greensreet, "Efficient self-timed interfaces for crossing clock domains," Proc. Intl. Symposium on Asynchronous Circuits and Systems, 2003, pp. 78-88